1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a method for fabricating a flash memory device, to decrease a cell size by forming a control gate within a minimum line width permitted in the fabrication process.
2. Discussion of the Related Art
In recent, a nonvolatile memory device of SONOS (Polysilicon-Oxide-Nitride-Oxide-Semiconductor) has great attentions in that it is possible to overcome the disadvantageous characteristics of other nonvolatile memory devices. In case of the nonvolatile memory device of SONOS, a top oxide layer serves as a potential barrier for access to electric charges through a gate. Also, the top oxide layer generates a new memory trap of great density to an interface with a nitride layer. Accordingly, it is possible to obtain a thin gate insulating layer, especially, thin nitride layer, in state of maintaining a memory window size, thereby obtaining a high-efficiency nonvolatile memory device having a low programmable voltage for record and erase and low power consumption.
Hereinafter, a related art SONOS-type flash memory device will be described with reference to the accompanying drawings. FIG. 1 is a cross-sectional view illustrating a related art SONOS-type flash memory device. FIG. 2 is a TEM photograph illustrating a related art Twin MONOS flash memory device. The commonly used flash memory device is largely classified into a stacked gate flash cell device having a stacked structure of a control gate and a floating gate, and an SONOS flash cell device in which a single gate and a gate dielectric are stacked as an ONO (oxide/nitride/oxide) structure.
FIG. 1 is a cross-sectional view illustrating a flash memory device having an SONOS cell structure, wherein a tunnel oxide layer 12-a trap nitride 13-a block oxide layer 14, having the ONO structure, are sequentially stacked on a p-type semiconductor substrate 11. Then, an n-type polysilicon gate 15 is stacked on the ONO layer 12, 13 and 14, and n-type impurity regions 16 and 17 are formed in the surface of the semiconductor substrate 11 at both sides of the n-type polysilicon gate 15, whereby the n-type impurity regions 16 and 17 are formed as source and drain regions.
A programming and erasing operation of the aforementioned SONOS-type flash memory device will be described as follows.
On a programming mode, a predetermined positive (+) voltage is applied to the drain region 17 and the gate 15, and the source region 16 and the semiconductor substrate (body) 11 are ground. Under this condition, according as a bias is applied, channel electrons are accelerated by a lateral electric field formed from the source region 16 to the drain region 17, whereby the channel electrons become hot electrons around the drain region 17. Also, the hot electrons are locally trapped to a trap level of the trap nitride 13 around the drain region 17 over the potential barrier of the tunnel oxide layer 12, thereby increasing a threshold voltage. This programming method is referred to as CHEI (Channel Hot Electron Injection).
On an erasing mode, a predetermined positive (+) voltage is applied to the drain region 17, and a predetermined negative (−) voltage is applied to the gate 15. Also, the source region 16 and the semiconductor substrate 11 are ground. Under this condition, according as a bias is applied, a depletion region is formed in the n-type drain region 17 by a high electric field formed in an overlap area between the drain region 17 and the gate 15. In the depletion region, pairs of electron and hole are formed by band to band tunneling. Then, the electron eacapes to the n-type region, and the hole is accelerated by the lateral electric field of the depletion region, whereby the hole is changed to a hot hole. The hot hole is injected and trapped to a valence band of the trap nitride 13 over an energy barrier formed between the tunnel oxide layer 12 and the semiconductor substrate 11, thereby performing the erasing mode lowing the threshold voltage. This erasing method is referred to as HHI (Hot Hole Injection).
The maximization of HCI (Hot Carrier Injection) effect is very important to the characteristics of the SONOS-type flash memory device, especially, it becomes more important with generalization of low power consumption device. In the SONOS-type flash memory device of FIG. 1, the HHI erasing method is used to remove the electrons injected on the erasing mode. In this case, it is very difficult to inject the holes corresponding to the number of the electrons injected on the erasing mode. Thus, some of the electrons injected on the erasing mode are accumulated due to incorrectness of hole injection, thereby degrading endurance of the device.
In order to solve these problems, another cell structure is shown as FIG. 2. In FIG. 2, control gates CG having sidewall spacer type are formed at both sides of a word line WL, and nitride storage sites are formed below the control gates CG (Embedded Twin MONOS Flash Memories with 4 ns and 15 ns Fast Access Times; Tomoko Ogura, Nori Orura, . . . ; 2003 Symposium on VLSI Circuits Digest of Technical Papers). In this structure, the condition of bias applied to the programming and erasing modes will be shown as Table 1.
TABLE 1OperationSelected WLSelected BLSelected CGElectricalMode(unselected)(unselected)(unselected)CharacteristicsRead1.8 V0 and 1.5 V1.8 and >2.8Ion > 60 μA/μm  (0 V)(1.8 V)(1.8 V)Ioff < 3.5 μA/μmProgram1.0 V4.5 and 0 V5.5 andIpgm < 2 μA/bit  (0 V)(1.8 V)>2.8 V Tpgm = 20 μs(1.8 V)Erase0 floating4.5 V −3 VIers < 2 nA/bithot hole(1.8 or 0 V)  (0 V)Ters = 10–100 ms
On the erasing mode by this bias condition, it is possible to improve efficiency of the hole injection by the control gate of the sidewall type, thereby improving endurance. However, the control gate of the sidewall type is formed outside a minimum line width (A) permitted in the fabrication process, thereby increasing a cell size. Thus, it is disadvantageous to miniaturization of the device and improvement of cell integration. Also, the control gate has the sidewall type by etch-back, thereby lowering yield.